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Mojo struct

AMDScheduleBarrierMask

@register_passable(trivial) struct AMDScheduleBarrierMask

Represents different instruction scheduling masks for AMDGPU scheduling instructions. These masks control which instructions can be reordered across the barrier.

Aliases​

  • NONE = AMDScheduleBarrierMask(0):
  • ALL_ALU = AMDScheduleBarrierMask(1):
  • VALU = AMDScheduleBarrierMask(2):
  • SALU = AMDScheduleBarrierMask(4):
  • MFMA = AMDScheduleBarrierMask(8):
  • ALL_VMEM = AMDScheduleBarrierMask(16):
  • VMEM_READ = AMDScheduleBarrierMask(32):
  • VMEM_WRITE = AMDScheduleBarrierMask(64):
  • ALL_DS = AMDScheduleBarrierMask(128):
  • DS_READ = AMDScheduleBarrierMask(256):
  • DS_WRITE = AMDScheduleBarrierMask(512):
  • TRANS = AMDScheduleBarrierMask(1024):

Implemented traits​

AnyType, CollectionElement, Copyable, ExplicitlyCopyable, Intable, Movable, UnknownDestructibility

Methods​

__init__​

@implicit __init__(value: Int) -> Self

__eq__​

__eq__(self, other: Self) -> Bool

__ne__​

__ne__(self, other: Self) -> Bool

__str__​

__str__(self) -> String

__int__​

__int__(self) -> Int