Mojo struct
OutputRegisterBuffer
struct OutputRegisterBuffer[dtype: DType, num_m_mmas: Int, num_n_mmas: Int, output_frag_size: Int]
Fields
- reg_tile (
LayoutTensor[dtype, Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), MutableAnyOrigin, address_space=AddressSpace(5)]):
Implemented traits
AnyType,
RegisterBuffer,
UnknownDestructibility
Aliases
__del__is_trivial
alias __del__is_trivial = True
reg_dtype
alias reg_dtype = dtype
reg_tile_layout
alias reg_tile_layout = Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size)
RegisterTileType
alias RegisterTileType = LayoutTensor[dtype, Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), MutableAnyOrigin, address_space=AddressSpace(5)]
Methods
__init__
__init__(out self)
get_dtype
vectorize
vectorize(self) -> LayoutTensor[dtype, coalesce(LayoutTensor._compute_tile_layout[True, dtype, Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), MutableAnyOrigin, AddressSpace(5), Layout(IntTuple(1), IntTuple(1)), _get_layout_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5)), _get_index_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5)), False, align_of[dtype](), 1, output_frag_size]()[1], True), MutableAnyOrigin, address_space=AddressSpace(5), element_layout=LayoutTensor._divide_tiles[True, dtype, Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), MutableAnyOrigin, AddressSpace(5), Layout(IntTuple(1), IntTuple(1)), _get_layout_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5)), _get_index_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5)), False, align_of[dtype](), 1, output_frag_size]()[0], layout_int_type=_get_layout_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5)), linear_idx_type=_get_index_type(Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), AddressSpace(5))]
Returns:
apply_softmax_denominator
apply_softmax_denominator(self, rowsum: LayoutTensor[dtype, layout, origin, address_space=address_space, element_layout=element_layout, layout_int_type=layout_int_type, linear_idx_type=linear_idx_type, masked=masked, alignment=alignment])
zero
zero(self)
get_reg_tile
get_reg_tile(self) -> LayoutTensor[dtype, Layout.row_major((num_n_mmas * num_m_mmas), output_frag_size), MutableAnyOrigin, address_space=AddressSpace(5)]
Returns:
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