Mojo struct
ScatterGatherAmd
struct ScatterGatherAmd[thread_layout: Layout, num_threads: Int = thread_layout.size(), thread_scope: ThreadScope = ThreadScope.BLOCK, block_dim_count: Int = 1]
AMD tile-based scatter-gather for DRAM-register data movement.
Parameters
- thread_layout (
Layout): Thread organization layout. - num_threads (
Int): Total threads (defaults to thread_layout size). - thread_scope (
ThreadScope): Thread execution scope (block or warp). - block_dim_count (
Int): Number of block dimensions.
Fields
- buffer (
AMDBufferResource):
Implemented traits
AnyType,
ImplicitlyDestructible
comptime members
__del__is_trivial
comptime __del__is_trivial = True
Methods
__init__
__init__(out self, tensor: LayoutTensor[tensor.dtype, tensor.layout, tensor.origin, address_space=tensor.address_space, element_layout=tensor.element_layout, layout_int_type=tensor.layout_int_type, linear_idx_type=tensor.linear_idx_type, masked=tensor.masked, alignment=tensor.alignment])
Initialize with a tensor.
Args:
- tensor (
LayoutTensor): Layout tensor for AMD buffer resource creation.
copy
copy(self, dst_reg_tile: LayoutTensor[dst_reg_tile.dtype, dst_reg_tile.layout, dst_reg_tile.origin, address_space=AddressSpace.LOCAL, element_layout=dst_reg_tile.element_layout, layout_int_type=dst_reg_tile.layout_int_type, linear_idx_type=dst_reg_tile.linear_idx_type, masked=dst_reg_tile.masked, alignment=dst_reg_tile.alignment], src_gmem_tile: LayoutTensor[src_gmem_tile.dtype, src_gmem_tile.layout, src_gmem_tile.origin, address_space=src_gmem_tile.address_space, element_layout=src_gmem_tile.element_layout, layout_int_type=src_gmem_tile.layout_int_type, linear_idx_type=src_gmem_tile.linear_idx_type, masked=src_gmem_tile.masked, alignment=src_gmem_tile.alignment], offset: Optional[UInt] = None)
Copy DRAM to registers.
Args:
- dst_reg_tile (
LayoutTensor): Destination register tile. - src_gmem_tile (
LayoutTensor): Source global memory tile. - offset (
Optional): Optional copy offset.
copy(self, dst_gmem_tile: LayoutTensor[dst_gmem_tile.dtype, dst_gmem_tile.layout, dst_gmem_tile.origin, address_space=dst_gmem_tile.address_space, element_layout=dst_gmem_tile.element_layout, layout_int_type=dst_gmem_tile.layout_int_type, linear_idx_type=dst_gmem_tile.linear_idx_type, masked=dst_gmem_tile.masked, alignment=dst_gmem_tile.alignment], src_reg_tile: LayoutTensor[src_reg_tile.dtype, src_reg_tile.layout, src_reg_tile.origin, address_space=AddressSpace.LOCAL, element_layout=src_reg_tile.element_layout, layout_int_type=src_reg_tile.layout_int_type, linear_idx_type=src_reg_tile.linear_idx_type, masked=src_reg_tile.masked, alignment=src_reg_tile.alignment])
Copy registers to DRAM.
Args:
- dst_gmem_tile (
LayoutTensor): Destination global memory tile. - src_reg_tile (
LayoutTensor): Source register tile.
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