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Mojo function
encode_f32_to_fp6
def encode_f32_to_fp6[width: SIMDLength, //, fmt: FP6Format](x: SIMD[DType.float32, width]) -> SIMD[DType.uint8, width]
Encodes float32 values to FP6 codes with round-to-nearest-even.
Expects x to already be divided by its block's E8M0 scale. Magnitudes
above the format maximum saturate; FP6 has no Inf or NaN encoding, so a
non-finite input has no faithful representation and the caller must screen
for it (an all-ones E8M0 block scale is the MX spec's NaN channel).
Two regimes, selected branch-free:
- Subnormal (
|x| < 2^(1 - bias)): the representable values form a uniform grid of stepS = 2^(1 - bias - M), so adding a magic2^23 * Sforces the hardware to round|x|onto that grid with the FPU's own round-to-nearest-even, and the difference from the magic's bit pattern is the mantissa code.|x|is bounded well below the magic, so the add never leaves the magic's binade. - Normal: round the float32 significand at bit
23 - Mwith the standard round-to-nearest-even integer add, then read the exponent and mantissa fields off the rounded pattern. Rounding that carries into the exponent is handled for free because the carry propagates through the full bit pattern before extraction.
Parameters:
- โwidth (
SIMDLength): SIMD width (lane count) of the input vector. - โfmt (
FP6Format): The FP6 encoding to produce.
Args:
- โx (
SIMD[DType.float32, width]): Scale-normalized values, one per lane. Must be finite.
Returns:
SIMD[DType.uint8, width]: One FP6 code per lane in the low 6 bits (0..63).