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Mojo function
copy_dram_to_local
def copy_dram_to_local[src_thread_layout: Layout, num_threads: Int = src_thread_layout.size(), thread_scope: ThreadScope = ThreadScope.BLOCK, block_dim_count: Int = Int(1), cache_policy: CacheOperation = CacheOperation.ALWAYS](dst: LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment], src: LayoutTensor[address_space=src.address_space, element_layout=src.element_layout, layout_int_type=src.layout_int_type, linear_idx_type=src.linear_idx_type, masked=src.masked, alignment=src.alignment], src_base: LayoutTensor[address_space=src_base.address_space, element_layout=src_base.element_layout, layout_int_type=src_base.layout_int_type, linear_idx_type=src_base.linear_idx_type, masked=src_base.masked, alignment=src_base.alignment], offset: Optional[Int] = None)
Efficiently copy data from global memory (DRAM) to registers for AMD GPUs.
This function implements an optimized memory transfer operation specifically for AMD GPU architectures. It utilizes the hardware's buffer_load intrinsic to efficiently transfer data from global memory to registers while handling bounds checking. The function distributes the copy operation across multiple threads for maximum throughput.
Notes:
- The offset calculation method significantly impacts performance. Current implementation optimizes for throughput over flexibility.
- This function is particularly useful for prefetching data into registers before performing computations, reducing memory access latency.
Constraints:
- Only supported on AMD GPUs.
- The destination element layout size must match the SIMD width.
- Source fragments must be rank 2 with known dimensions.
Parameters:
- βsrc_thread_layout (
Layout): The layout used to distribute the source tensor across threads. This determines how the workload is divided among participating threads. - βnum_threads (
Int): Total number of threads in the thread block. Threads beyondsrc_thread_layout.size()will be disabled and not participate in the copy operation. - βthread_scope (
ThreadScope): Defines whether operations are performed atBLOCKorWARPlevel.BLOCKscope involves all threads in a thread block, whileWARPscope restricts operations to threads within the same warp. Defaults toThreadScope.BLOCK. - βblock_dim_count (
Int): The number of dimensions in the thread block. - βcache_policy (
CacheOperation): The cache policy to use for the copy operation. Defaults toCacheOperation.ALWAYS.
Args:
- βdst (
LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment]): The destination tensor in register memory (LOCAL address space). - βsrc (
LayoutTensor[address_space=src.address_space, element_layout=src.element_layout, layout_int_type=src.layout_int_type, linear_idx_type=src.linear_idx_type, masked=src.masked, alignment=src.alignment]): The source tensor in global memory (DRAM) to be copied. - βsrc_base (
LayoutTensor[address_space=src_base.address_space, element_layout=src_base.element_layout, layout_int_type=src_base.layout_int_type, linear_idx_type=src_base.linear_idx_type, masked=src_base.masked, alignment=src_base.alignment]): The original global memory tensor from which src is derived. This is used to construct the buffer struct required by AMD'sbuffer_loadintrinsic. - βoffset (
Optional[Int]): The offset in the global memory.
def copy_dram_to_local[src_thread_layout: Layout, num_threads: Int = src_thread_layout.size(), thread_scope: ThreadScope = ThreadScope.BLOCK, block_dim_count: Int = Int(1), cache_policy: CacheOperation = CacheOperation.ALWAYS](dst: LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment], src_iter: LayoutTensorIter[address_space=src_iter.address_space, alignment=src_iter.alignment, circular=src_iter.circular, axis=src_iter.axis, layout_int_type=src_iter.layout_int_type, linear_idx_type=src_iter.linear_idx_type, masked=src_iter.masked], bounds: UInt32)
Efficiently copy data from global memory (DRAM) to registers for AMD GPUs.
This function implements an optimized memory transfer operation specifically for AMD GPU architectures. It utilizes the hardware's buffer_load intrinsic to efficiently transfer data from global memory to registers while handling bounds checking. The function distributes the copy operation across multiple threads for maximum throughput.
Notes:
- The offset calculation method significantly impacts performance. Current implementation optimizes for throughput over flexibility.
- This function is particularly useful for prefetching data into registers before performing computations, reducing memory access latency.
Constraints:
- Only supported on AMD GPUs.
- The destination element layout size must match the SIMD width.
- Source fragments must be rank 2 with known dimensions.
Parameters:
- βsrc_thread_layout (
Layout): The layout used to distribute the source tensor across threads. This determines how the workload is divided among participating threads. - βnum_threads (
Int): Total number of threads in the thread block. Threads beyondsrc_thread_layout.size()will be disabled and not participate in the copy operation. - βthread_scope (
ThreadScope): Defines whether operations are performed atBLOCKorWARPlevel.BLOCKscope involves all threads in a thread block, whileWARPscope restricts operations to threads within the same warp. Defaults toThreadScope.BLOCK. - βblock_dim_count (
Int): The number of dimensions in the thread block. - βcache_policy (
CacheOperation): The cache policy to use for the copy operation. Defaults toCacheOperation.ALWAYS.
Args:
- βdst (
LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment]): The destination tensor in register memory (LOCAL address space). - βsrc_iter (
LayoutTensorIter[address_space=src_iter.address_space, alignment=src_iter.alignment, circular=src_iter.circular, axis=src_iter.axis, layout_int_type=src_iter.layout_int_type, linear_idx_type=src_iter.linear_idx_type, masked=src_iter.masked]): The source tensor iterator. - βbounds (
UInt32): Bounds of the buffer, based on the ptr of the src_iter.
def copy_dram_to_local[src_thread_layout: Layout, num_threads: Int = src_thread_layout.size(), thread_scope: ThreadScope = ThreadScope.BLOCK, block_dim_count: Int = Int(1)](dst: LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment], src: LayoutTensor[address_space=src.address_space, element_layout=src.element_layout, layout_int_type=src.layout_int_type, linear_idx_type=src.linear_idx_type, masked=src.masked, alignment=src.alignment])
Efficiently copy data from global memory (DRAM) to registers.
This function implements an optimized memory transfer operation from global memory to register memory. It distributes the copy operation across multiple threads for maximum throughput while handling bounds checking for safety.
Constraints:
- The source tensor must be in GLOBAL address space (DRAM).
- The destination tensor must be in LOCAL address space (registers).
- Both tensors must have compatible data types.
Parameters:
- βsrc_thread_layout (
Layout): The layout used to distribute the source tensor across threads. This determines how the workload is divided among participating threads. - βnum_threads (
Int): Total number of threads in the thread block. Threads beyondsrc_thread_layout.size()will be disabled and not participate in the copy operation. - βthread_scope (
ThreadScope): Defines whether operations are performed atBLOCKorWARPlevel.BLOCKscope involves all threads in a thread block, whileWARPscope restricts operations to threads within the same warp. Defaults toThreadScope.BLOCK. - βblock_dim_count (
Int): The number of dimensions in the thread block.
Args:
- βdst (
LayoutTensor[address_space=dst.address_space, element_layout=dst.element_layout, layout_int_type=dst.layout_int_type, linear_idx_type=dst.linear_idx_type, masked=dst.masked, alignment=dst.alignment]): The destination tensor in register memory (LOCAL address space). - βsrc (
LayoutTensor[address_space=src.address_space, element_layout=src.element_layout, layout_int_type=src.layout_int_type, linear_idx_type=src.linear_idx_type, masked=src.masked, alignment=src.alignment]): The source tensor in global memory (DRAM).