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Mojo function

rope_split_store_paged_ragged

def rope_split_store_paged_ragged[dtype: DType, freq_dtype: DType, q_out_dtype: DType = dtype, target: StringSlice[ImmStaticOrigin] = StringSlice("cpu"), interleaved: Bool = True](qkv: TileTensor[dtype, Storage=qkv.Storage, address_space=qkv.address_space, linear_idx_type=qkv.linear_idx_type], input_row_offsets: TileTensor[DType.uint32, Storage=input_row_offsets.Storage, address_space=input_row_offsets.address_space, linear_idx_type=input_row_offsets.linear_idx_type], freqs_cis: TileTensor[freq_dtype, Storage=freqs_cis.Storage, address_space=freqs_cis.address_space, linear_idx_type=freqs_cis.linear_idx_type], kv_collection: PagedKVCacheCollection[scale_dtype_=kv_collection.scale_dtype_, quantization_granularity_=kv_collection.quantization_granularity_], layer_idx: UInt32, q_output: TileTensor[q_out_dtype, Storage=q_output.Storage, address_space=q_output.address_space, linear_idx_type=q_output.linear_idx_type], ctx: DeviceContext)

Rope+split+store with paged KV cache collection.

Parameters:

  • ​dtype (DType): Element type of the QKV input buffer.
  • ​freq_dtype (DType): Element type of the freqs_cis RoPE frequency table.
  • ​q_out_dtype (DType): Element type of the roped Q output buffer (defaults to dtype).
  • ​target (StringSlice[ImmStaticOrigin]): Compile target backend, for example "gpu" or "cpu" (defaults to "cpu").
  • ​interleaved (Bool): Whether RoPE uses the interleaved real/imag layout (defaults to True).

Args:

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