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Mojo function

dispatch_qslice_conv3d_sm100

def dispatch_qslice_conv3d_sm100[input_type: DType, filter_type: DType, output_type: DType, //, filter_is_fcrs: Bool = False, maybe_epilogue_func: Optional[def[dtype: DType, rank: Int, width: SIMDLength, alignment: Int = Int(1)](IndexList[rank], SIMD[dtype, width]) capturing thin -> None] = None](input: TileTensor[input_type, Storage=input.Storage, address_space=input.address_space, linear_idx_type=input.linear_idx_type], filter: TileTensor[filter_type, Storage=filter.Storage, address_space=filter.address_space, linear_idx_type=filter.linear_idx_type], output: TileTensor[output_type, Storage=output.Storage, address_space=output.address_space, linear_idx_type=output.linear_idx_type], stride: IndexList[Int(3)], dilation: IndexList[Int(3)], symmetric_padding: IndexList[Int(3)], num_groups: Int, ctx: DeviceContext) -> Bool

Try to dispatch a 3-D conv as Q × SM100 2-D conv calls with a dedicated fp32 accumulator.

Parameters:

input_type (DType): The element type of input (inferred). The gate requires DType.bfloat16.
filter_type (DType): The element type of filter (inferred).
output_type (DType): The element type of output (inferred). The gate requires DType.bfloat16.
filter_is_fcrs (Bool): Whether filter is laid out as FCQRS rather than QRSCF (defaults to False). The gate requires False because a fixed-q FCQRS slab is non-contiguous.
maybe_epilogue_func (Optional[def[dtype: DType, rank: Int, width: SIMDLength, alignment: Int = Int(1)](IndexList[rank], SIMD[dtype, width]) capturing thin -> None]): Optional 5-D elementwise epilogue fused into the final fp32-to-output_type write (defaults to None).

Args:

input (TileTensor[input_type, Storage=input.Storage, address_space=input.address_space, linear_idx_type=input.linear_idx_type]): Rank-5 input tensor in NDHWC layout.
filter (TileTensor[filter_type, Storage=filter.Storage, address_space=filter.address_space, linear_idx_type=filter.linear_idx_type]): Rank-5 filter tensor in QRSCF layout, shaped [Q, R, S, C_in, C_out].
output (TileTensor[output_type, Storage=output.Storage, address_space=output.address_space, linear_idx_type=output.linear_idx_type]): Rank-5 mutable output tensor in NDHWC layout.
stride (IndexList[Int(3)]): Per-axis stride for the (D, H, W) dimensions. The gate requires (1, 1, 1).
dilation (IndexList[Int(3)]): Per-axis dilation for the (D, H, W) dimensions. The gate requires (1, 1, 1).
symmetric_padding (IndexList[Int(3)]): Symmetric padding for the (D, H, W) dimensions. Temporal (D) padding must be zero.
num_groups (Int): Number of convolution groups. The gate requires 1.
ctx (DeviceContext): Device context used for buffer allocation and kernel launches.

Returns:

Bool