For the complete documentation index, see llms.txt. Markdown versions of all pages are available by appending .md to any URL (e.g. /max/get-started.md).
Mojo struct
TileScheduler
struct TileScheduler[num_stages: Int, cluster_shape: IndexList[Int(3), element_type=DType.uint32] = Index[Int, Int, Int, dtype=DType.uint32](Int(1), Int(1), Int(1)), rasterize_order: RasterOrder = RasterOrder.AlongM, block_swizzle_size: Int = Int(8)]
Schedules output-tile work across CTAs and clusters via Cluster Launch Control.
Owns the CLC response, full/empty barrier, and throttle pipeline state used to distribute and pace work for SM100 structured matmul kernels. Provides work iterators for both worker warps and the scheduler warp, along with rasterization and block-swizzle remapping of cluster-local tile coordinates to global output-matrix coordinates.
Parametersβ
- βnum_stages (
Int): Number of CLC pipeline stages for work distribution. - βcluster_shape (
IndexList[Int(3), element_type=DType.uint32]): Cluster tile counts as(m, n, k)(defaults to(1, 1, 1)). - βrasterize_order (
RasterOrder): Order CLC rasterizes tiles across the cluster grid (defaults toRasterOrder.AlongM). - βblock_swizzle_size (
Int): Block swizzle factor for tile remapping, one of 0, 1, 2, 4, or 8 (defaults to 8).
Fieldsβ
- βcluster_dim (
StaticTuple[Int32, Int(3)]): - βlog_cluster_dim_m (
FastDiv[DType.uint32]): - βlog_cluster_dim_n (
FastDiv[DType.uint32]): - βlog_cluster_dim_k (
FastDiv[DType.uint32]): - βclc_response (
Pointer[UInt128, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False]): - βfull_mbar (
Pointer[SharedMemBarrier, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False]): - βempty_mbar (
Pointer[SharedMemBarrier, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False]): - βthrottle_pipeline (
TileScheduler[num_stages, cluster_shape, rasterize_order, block_swizzle_size].ThrottlePipeline):
Implemented traitsβ
AnyType,
Copyable,
ImplicitlyCopyable,
ImplicitlyDeletable,
Movable,
RegisterPassable,
TrivialRegisterPassable
comptime membersβ
ClcBarrierArrayβ
comptime ClcBarrierArray = SMemArray[SharedMemBarrier, num_stages]
ClcResponseArrayβ
comptime ClcResponseArray = SMemArray[UInt128, num_stages]
cluster_sizeβ
comptime cluster_size = (Int((mul cluster_shape[Int(0)], cluster_shape[Int(1)])) * cluster_shape[Int(2)])
log_cluster_kβ
comptime log_cluster_k = FastDiv(cluster_shape[Int(2)])
log_cluster_mβ
comptime log_cluster_m = FastDiv(cluster_shape[Int(0)])
log_cluster_nβ
comptime log_cluster_n = FastDiv(cluster_shape[Int(1)])
ThrottleBarrierArrayβ
comptime ThrottleBarrierArray = SMemArray[SharedMemBarrier, (num_stages * Int(2))]
ThrottlePipelineβ
comptime ThrottlePipeline = ProducerConsumerPipeline[num_stages]
Methodsβ
__init__β
def __init__(cluster_dim: StaticTuple[Int32, Int(3)], clc_response: SMemArray[UInt128, num_stages], clc_full: SMemArray[SharedMemBarrier, num_stages], clc_empty: SMemArray[SharedMemBarrier, num_stages], clc_throttle: SMemArray[SharedMemBarrier, (num_stages * Int(2))]) -> Self
Initialize from typed barrier arrays.
Args:
- βcluster_dim (
StaticTuple[Int32, Int(3)]): Grid cluster dimensions as(m, n, k)used for fast division rasterization. - βclc_response (
SMemArray[UInt128, num_stages]): Shared memory array storing CLC response payloads. - βclc_full (
SMemArray[SharedMemBarrier, num_stages]): Barriers signaled when CLC response data is ready. - βclc_empty (
SMemArray[SharedMemBarrier, num_stages]): Barriers signaled when a response slot is available. - βclc_throttle (
SMemArray[SharedMemBarrier, (num_stages * Int(2))]): Barriers for the throttle pipeline pacing the scheduler against the load warp.
init_throttle_barriersβ
static def init_throttle_barriers(storage_ptr: Pointer[SharedMemBarrier, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False], producer_arv_count: Int32, consumer_arv_count: Int32)
Initialize throttle pipeline barriers. Called once by elect_one thread.
Args:
- βstorage_ptr (
Pointer[SharedMemBarrier, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False]): Shared memory storage for the throttle barriers. - βproducer_arv_count (
Int32): Arrival count for producer-side barriers. - βconsumer_arv_count (
Int32): Arrival count for consumer-side barriers.
work_info_from_clc_responseβ
static def work_info_from_clc_response(result: Pointer[UInt128, MutUntrackedOrigin, address_space=AddressSpace.SHARED, _safe=False]) -> WorkInfo
Returns:
work_info_from_clusterβ
static def work_info_from_cluster(work_info: WorkInfo, cluster_dim: StaticTuple[Int32, Int(3)], log_cluster_dim_m: FastDiv[DType.uint32], log_cluster_dim_n: FastDiv[DType.uint32]) -> WorkInfo
Returns:
initial_work_infoβ
fetch_next_workβ
def fetch_next_work(self, work_info: WorkInfo, consumer_state: PipelineState[num_stages]) -> WorkInfo
Returns:
throttle_signalβ
def throttle_signal(mut self, is_first_cta_in_cluster: Bool)
Signal CLC throttle if this is the first CTA in cluster.
The Load warp acts as producer for CLC throttle, signaling that it has started processing a new work item. This prevents the scheduler from getting too far ahead.
Args:
- βis_first_cta_in_cluster (
Bool): Only first CTA signals to avoid duplicates.
wait_and_advance_workβ
def wait_and_advance_work[work_origin: MutOrigin, //](self, ref[num_stages] work_info: WorkInfo, mut consumer_state: PipelineState[num_stages]) -> WaitAndAdvanceContext[work_origin]
Wait for next work from CLC and advance.
Encapsulates the CLC barrier wait (called on scheduler directly).
Usage: with scheduler.wait_and_advance_work(work_info, state) as current: do_mma(current) # After: work_info updated to next value
Parameters:
- βwork_origin (
MutOrigin): Memory origin of thework_inforeference (inferred).
Args:
- βwork_info (
WorkInfo): Reference to the current work item, updated to the next work item on context exit. - βconsumer_state (
PipelineState[num_stages]): Consumer pipeline state, stepped after the fetch.
Returns:
WaitAndAdvanceContext[work_origin]
work_iteratorβ
def work_iterator(self) -> WorkIterator[num_stages, cluster_shape, rasterize_order, block_swizzle_size]
Create a per-warp work iterator using next-style iteration.
Each warp should create its own work iterator. The iterator owns work_info and pipeline state internally.
Usage: var work_iter = scheduler.work_iterator() for current in work_iter: scheduler.throttle_signal(ctx.is_first_cta_in_cluster) do_work(current)
Returns:
WorkIterator[num_stages, cluster_shape, rasterize_order, block_swizzle_size]
scheduler_iteratorβ
def scheduler_iterator(self) -> SchedulerWorkIterator[num_stages, cluster_shape, rasterize_order, block_swizzle_size]
Create iterator for Scheduler warp (owns work_info and both pipeline states).
The Scheduler warp uniquely needs to both consume work responses and produce new work requests. This iterator owns everything internally.
Usage: var sched_iter = scheduler.scheduler_iterator() for _ in sched_iter: sched_iter.signal_and_advance() sched_iter.drain()
Returns:
SchedulerWorkIterator[num_stages, cluster_shape, rasterize_order, block_swizzle_size]
advance_to_next_workβ
def advance_to_next_work(self, mut clc_state: PipelineState[num_stages]) -> PipelineState[num_stages]
Returns:
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