For the complete documentation index, see llms.txt. Markdown versions of all pages are available by appending .md to any URL (e.g. /max/get-started.md).

Mojo function

matmul_swiglu_dispatch_sm100

def matmul_swiglu_dispatch_sm100[config: FusedSwiGLUMatmulConfig[config.a_type, config.b_type, config.c_type], pdl_level: PDLLevel = PDLLevel(Int(0))](c_out: TileTensor[DType.bfloat16, address_space=c_out.address_space, linear_idx_type=c_out.linear_idx_type], a: TileTensor[DType.bfloat16, Storage=a.Storage, address_space=a.address_space, linear_idx_type=a.linear_idx_type], b: TileTensor[DType.bfloat16, Storage=b.Storage, address_space=b.address_space, linear_idx_type=b.linear_idx_type], ctx: DeviceContext, bias_ptr: OptionalReg[Pointer[BFloat16, ImmutAnyOrigin, _safe=False]] = None)

Dispatch fused GEMM+SwiGLU to SM100 kernel with given config.

Parameters:

config (FusedSwiGLUMatmulConfig[config.a_type, config.b_type, config.c_type]): Fully specialized FusedSwiGLUMatmulConfig carrying the MMA shape, cluster shape, swizzle modes, pipeline stage counts, AB_swapped orientation, and use_bias flag used to specialize the kernel.
pdl_level (PDLLevel): Programmatic Dependency Launch level controlling inter-grid overlap on the launch (defaults to PDLLevel.OFF).

Args:

c_out (TileTensor[DType.bfloat16, address_space=c_out.address_space, linear_idx_type=c_out.linear_idx_type]): [M, H] BF16 output tensor (H = N/2).
a (TileTensor[DType.bfloat16, Storage=a.Storage, address_space=a.address_space, linear_idx_type=a.linear_idx_type]): [M, K] BF16 input activations.
b (TileTensor[DType.bfloat16, Storage=b.Storage, address_space=b.address_space, linear_idx_type=b.linear_idx_type]): [N, K] BF16 pre-permuted weights (N = 2H, transposed). When config.AB_swapped is False, b is permuted on its N axis so adjacent (gate, up) pairs are at rows (2i, 2i+1). When config.AB_swapped is True, b is permuted on its N axis with stride-8 row blocks (see kernel docs for the exact formula).
ctx (DeviceContext): Device context for kernel launch.
bias_ptr (OptionalReg[Pointer[BFloat16, ImmutAnyOrigin, _safe=False]]): Optional [N=2H] BF16 bias (interleaved gate/up pairs). Ignored when config.use_bias is False.